1. Field of Invention
Embodiments of the present invention disclosed herein generally relate to semiconductor devices and methods for fabricating the same and, more particularly, to a semiconductor device having charge storage patterns and a method for fabricating the same.
2. Description of the Related Art
Semiconductor devices such as non-volatile memory devices retain stored data even when a power supply is cut off. Also, non-volatile memory devices such as flash memory can perform a program operation in units of pages or multi-bits and an erase operation in units of blocks or sectors, thus providing an improved operation speed. Non-volatile memory devices are widely used in a variety of devices such as digital mobile communication devices, digital cameras, LAN switches, and PC cards for notebook computers.
Non-volatile memory devices are generally classified as a floating gate type and a charge trap type, depending on the type charge storage layer incorporated therein. Floating gate non-volatile memory devices accumulate charges in a floating gate and charge trap non-volatile memory devices accumulates charges in a trap formed in a dielectric layer such as a silicon nitride layer. Floating gate non-volatile memory devices are limited in reducing a cell size and needs high voltages for program and erase operations. On the other hand, the charge trap non-volatile memory device is advantageous for high integration and can operate at low voltage.
Problems related to inter-device isolation, limited active region, and data retention characteristics must be solved to achieve high integration of charge trap memory devices.
FIG. 1 is a gate-direction sectional view of a conventional SONOS non-volatile memory device with extended active regions.
Referring to FIG. 1, the conventional SONOS non-volatile memory device includes a trench isolation layer 15 recessed below an upper surface of a semiconductor substrate 10. Therefore, a side surface of the semiconductor substrate 10 can be used as an active region, thereby forming an extended active region. A tunnel isolation layer 20, a charge trap layer 30, a blocking insulating layer 40 preventing loss of charges and a gate electrode 50 are formed on the extended active region and the isolation layer 15. However, when the distance between adjacent cells is reduced in order to improve the integration of the non-volatile memory device with the extended active region, trapped charges can be transferred between the adjacent cells to change stored data. Moreover, the distance between the adjacent cells is further reduced because the tunnel isolation layer 20, the charge trap layer 30, and the blocking insulating layer 40 are also formed the side surface of the extended active region.